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2001
8. Yang-Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, Erik Anderson, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu, "Sub-20nm CMOS FinFET Technologies," IEEE IEDM Technical Digest, pp. 421-24, Washington DC, USA, Dec. 2-5, 2001. [PDF]

7. Leland Chang, Kevin J. Yang, Tee-Chia Yeo, Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu, "Reduction of Direct- Tunneling Gate Leakage Current in Double-Gate and Ultra-Thin Body MOSFETs," IEEE IEDM Technical Digest, pp. 99-102, Washington DC, USA, Dec. 2-5, 2001. [PDF]

6. Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu, "Spacer FinFET: Nano-scale CMOS Technology for the Terabit Era," Proceedings of International Semiconductor Device Research Symposium, pp. 543-546, Washington DC, USA, Dec. 5-7, 2001. (Secondly Best Student Paper Award) [PDF]

5. N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, C. Hu, "Quasi-Planar FinFETs with Selectively Grown Germanium Raised Source/Drain," IEEE International SOI Conference Proceedings, pp. 111-112, Durango, USA, Oct. 1-4, 2001. (Best Student Paper Award) [PDF]

4. Stephen H. Tang, Leland Chang, Nick Lindert, Yang-Kyu Choi, Wen-Chin Lee, Xuejue Huang, Vivek Subramanian, Jeffrey Bokor, Tsu-Jae King, and Chenming Hu, "FinFET-A quasi-Planar Double-Gate MOSFET," 2001 IEEE International Solid-State Circuit Conference Digest of Technical Papers, pp. 118-119, Hammamet, Tunisia, July 3-5, 2001. [PDF]

3. Yang-Kyu Choi, Daewon Ha, Tsu-Jae King and Chenming Hu, "Threshold Voltage Shift by Quantum Confinement in Ultra-thin Body Device," 59th IEEE Device Research Conference Proceedings, pp. 85-86, Notre Dame, USA, Jun. 25-27, 2001. [PDF]

2. Nick Lindert, Yang-Kyu Choi, Leland Chang, Erik Anderson, Wenchin Lee, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu, "Quasi-Planar NMOS FinFETs with sub-100nm Gate Lengths," 59th IEEE Device Research Conference Proceedings, pp. 26-27, Notre Dame, USA, Jun. 25 - 27, 2001. [PDF]

1. Yang-Kyu Choi, Daewon Ha, Tsu-Jae King, and Chenming Hu, "Ultra-Thin Body PMOSFETs with Selectively Deposited Ge Source/Drain," 2001 IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 19-20, Kyoto, Japan, Jun. 12 - 14, 2001. [PDF]